Arjun Rajagopal, Anand Rajaram, Raguram Damodaran, Frank Cano, Srinivas Swaminathan, Clive Bittlestone, Mark Terry, Mark Mason, Yajun Ran, Haizhou Chen, Robert Ritchie, Bala Kasthuri, Jac Condella, Philippe Hurat, and Nishath Verghese, “Context analysis and validation of lithography induced systematic variations in 65nm designs”, Proc. SPIE 6925, 69250A (2008), DOI:10.1117/12.778836

Sean O’Brien, Robert Soper, Shane Best, and Mark Mason, “Rules based process window OPC”, Proc. SPIE 6925, 69251C (2008), DOI:10.1117/12.772790

Mark Mason, Shane Best, Gary Zhang, Mark Terry, and Robert Soper, “Finding the needle in the haystack: using full-chip process window analysis to qualify competing SRAF placement strategies for 65 nm”, Proc. SPIE 6349, 63491X (2006), DOI:10.1117/12.687008

Zhijian Lu, Chi-Chien Ho, Mark Mason, Andrew Anderson, Randy Mckee, Ricky Jackson, Cynthia Zhu, and Mark Terry, “Challenges and solutions for trench lithography beyond 65nm node”, Proc. SPIE 6156, 615617 (2006), DOI:10.1117/12.659242

Mark Mason, Christopher J. Progler, Patrick Martin, Young-Mog Ham, Brian Dillon, Robert Pack, Mitch Heins, John Gookassian, John Garcia, and Victor Boksha, “Mask design rules (45nm): time for standardization”, Proc. SPIE 5992, 59920D (2005), DOI:10.1117/12.633180

Scott Jessen, Mark Mason, Sean O’Brien, Mark Terry, Robert Soper, and Thomas Wolf, “Design rule considerations for 65-nm node contact using off axis illumination”, Proc. SPIE 5756, 274 (2005), DOI:10.1117/12.600005

Mark E. Mason, “The rising cost and complexity of RETs”, Proc. SPIE 5379, 10 (2004), DOI:10.1117/12.546794

Sean C. O’Brien, Tom Aton, Mark E. Mason, Carl Vickery, and John N. Randall, “OPC on real-world circuitry”, Proc. SPIE 5042, 107 (2003), DOI:10.1117/12.485484

Mark E. Mason, John N. Randall, and Keeho Kim, “Manufacturability of 248-nm phase-shift lithography for 100-nm transistors”, Proc. SPIE 4000, 1347 (2000), DOI:10.1117/12.388971

Keeho Kim, Mark E. Mason, John N. Randall, and Won D. Kim, “Process capability analysis of DUV alternating PSM and DUV attenuated PSM lithography for 100-nm gate fabrication”, Proc. SPIE 4000, 132 (2000), DOI:10.1117/12.388957

Mark E. Mason and Robert A. Soper, “Cross-sectional critical shape error: a novel methodology for quantifying process simulation accuracy”, Proc. SPIE 3334, 729 (1998), DOI:10.1117/12.310806

Mark E. Mason, Robert A. Soper, R. Mark Terry, and Chris A. Mack, “Process-specific tuning of lithography simulation tools”, Proc. SPIE 3051, 491 (1997), DOI:10.1117/12.275981

Amitava Chatterjee, Mark E. Mason, K. Joyner, Daty Rogers, Doug Mercer, John Kuehne, A. L. Esquivel, P. Mei, Suhail S. Murtaza, Kelly J. Taylor, Iqbal Ali, S. Nag, Sean C. O’Brien, S. Ashburn, and Ih-Chin Chen, “Study of integration issues in shallow trench isolation for deep submicron CMOS technologies”, Proc. SPIE 2875, 39 (1996), DOI:10.1117/12.250874

Mark E. Mason, Robert A. Soper, and Cesar M. Garza, Sr., “Improved method for the automated determination of E[sub 0] for lithography SPC”, Proc. SPIE 2726, 847 (1996), DOI:10.1117/12.240956

Mark Terry, Gary Zhang, George Lu, Simon Chang, Tom Aton, Robert Soper, Mark Mason, Shane Best, Bill Dostalik, Stefan Hunsche, Jiang Wei Li, Rongchun Zhou, Mu Feng, and Jim Burdorf, “Process window and interlayer aware OPC for the 32-nm node”, Proc. SPIE 6520, 65200S (2007), DOI:10.1117/12.714442

Scott Jessen, Mark Terry, Mark Mason, Sean O’Brien, Robert Soper, Willie Yarbrough, and Thomas Wolf, “Improving asymmetric printing and low margin using custom illumination for contact hole lithograph”, Proc. SPIE 6156, 615616 (2006), DOI:10.1117/12.660120

Mark Ma, Hyesook Hong, Yong Seok Choi, Chi-Chien Ho, Mark Mason, and Randy McKee, “Design, mask, and manufacturability”, Proc. SPIE 5567, 137 (2004), DOI:10.1117/12.569309

Gary Zhang, Mark Terry, Sean O’Brien, Robert Soper, Mark Mason, Won Kim, Changan Wang, Steven Hansen, Jason Lee, and Joe Ganeshan, “65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features”, Proc. SPIE 5754, 760 (2004), DOI:10.1117/12.600409

John N. Randall, Christopher C. Baum, Keeho Kim, and Mark E. Mason, “Mask error factor impact on the 130-nm node”, Proc. SPIE 4000, 594 (2000), DOI:10.1117/12.389049

Lowell K. Siewert, Andrew R. Mikkelson, Roxann L. Engelstad, Edward G. Lovell, Mark E. Mason, and R. S. Mackay, “Influence of film stress on advanced optical reticle distortions”, Proc. SPIE 4000, 1594 (2000), DOI:10.1117/12.389008

Andrew R. Mikkelson, Roxann L. Engelstad, Edward G. Lovell, Theodore M. Bloomstein, and Mark E. Mason, “Mechanical distortions in advanced optical reticles”, Proc. SPIE 3676, 744 (1999), DOI:10.1117/12.351143

James D. Legg, Mark E. Mason, Roger T. Williams, and Mark H. Weichold, “Improved monolithic vacuum field emission diodes”, J. Vac. Sci. Technol. B 12, 666 (1994), DOI:10.1116/1.587366

Mark H. Weichold, James D. Legg, Mark E. Mason, and Thomas C. James, “Manufacturable vacuum field emission diodes”, J. Vac. Sci. Technol. B 11, 505 (1993), DOI:10.1116/1.586851