Press

Articles and Quotes

 

Ed Sperling, “Experts At The Table: Improving Yield: Yield”, Semiconductor Manufacturing & Design, November 7th, 2011 http://semimd.com/blog/tag/texas-instruments/

 

Ed Sperling, “Experts At The Table: Improving Yield: Texas Instruments”, Semiconductor Manufacturing & Design, October 29, 2012 http://semimd.com/blog/tag/texas-instruments/

 

“Synopsys’ DFM Environment Selected by Texas Instruments for Design and Process Development for the 65-Nanometer Node and Beyond,” Synopsys, Inc., EDACafe, June 7, 2012

“Synopsys phase-shift technology allows us to tightly control lithography resolution and enhance yields on our high-performance chips,” said Mark Mason, resolution enhancement technology manager, Texas Instruments. “Synopsys’ mask synthesis solutions offer the critical dimension accuracy and near-linear scalability that we require to meet the complex data processing needs for our advanced 65- and 45-nanometer technology.” http://news.synopsys.com/index.php?s=43&item=284

 

Ed Sperling, “Experts At The Table: Improving Yield: PDF Solutions”, Semiconductor Manufacturing & Design, November 21, 2011 http://semimd.com/blog/tag/pdf-solutions/

 

Ed Sperling, “Experts At The Table: Improving Yield: Texas Instruments”, Semiconductor Manufacturing & Design, October 27, 2011 http://semimd.com/blog/tag/texas-instruments/page/2/

 

“Si2 Announces Donation of DRC+ from GLOBALFOUNDRIES,” Business Wire, October 20, 2011

“We are excited to see the increasing momentum of the DFMC,” says Mark Mason, director for Design Data Integration at Texas Instruments. “TI has already taped out several circuits using OpenDFM rules and we are seeing return on our investment in the OpenDFM standard in the form of interoperability and reuse.” TI reports that they are planning to use OpenDFM’s DRC standard as the baseline for several of their production flows. “We are currently moving our entire 28 nm Wireless platform DRC infrastructure to the OpenDFM standard, and plan to use it at 20 nm as well,” Mason said. “OpenDFM is already paying off for TI and the addition of DRC+ capabilities is very exciting.” http://www.businesswire.com/news/home/20111020005541/en/Si2-Ann.

 

“Si2 Releases OpenDFM 1.0 Physical Verification Standard,” MCADCafe, November 9, 2010

At a recent conference in Santa Clara, Mark Mason, Director of Design Data Integration for Texas Instruments, commented that Texas Instruments has demonstrated coverage, performance and accuracy of OpenDFM 1.0, working with all major EDA vendors. No loss of performance versus native code was observed, and all vendors passed the OpenDFM test cases developed by TI and contributed to Si2. He also stated that he believed OpenDFM 1.0 is verified, and that TI intends to implement it into production as soon as possible. For details on his comments, see this link: http://www.si2.org/events_dir/2010/confall10/7.pdf

http://www10.mcadcafe.com/nbc/articles/view_article.php?articleid=885959&interstitial_displayed=Yes

 

Kayvan Sadra*a, Mark Terrya, Arjun Rajagopala, Robert A. Sopera, Donald Kolarika, Tom Atona, Brian Hornunga, Rajesh Khamankara,Philippe Huratb, Bala Kasthurib, Yajun Ranb, Nishath Vergheseb, “Variations in timing and leakage power of 45nm library cells due to lithography and stress effects,” Proc. of SPIE Vol. 7275 72750K-10,(2008) 144.206.159.178/ft/CONF/16429570/16429584.pdf

 

Mark Mason,“DFM EDA Technology: A Lithographic Perspective”, 2007 Symposium on VLSI Technology Digest of Technical Papers http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04339739

 

Tom Cheyney, “Will DFM become the lingua franca of the chip world?” Micro Magazine.com, (2007)

At Semicon West in July, SEMI sponsored a Fab Managers Forum conference on design for manufacturing that brought together presenters from the design, manufacturing, and equipment segments to discuss these issues. Mark Mason, RET manager at Texas Instruments, told attendees that “DFM is no longer just a nice thing to have. First-pass success is expected.” http://micromagazine.fabtech.org/archive/05/10/industrynews-lead.html

 

Mark Terry; Gary Zhang; George Lu; Simon Chang; Tom Aton; Robert Soper; Mark Mason; Shane Best; Bill Dostalik; Stefan Hunsche; Jiang Wei Li; Rongchun Zhou; Mu Feng; Jim BurdorfProcess window and interlayer aware OPC for the 32-nm node,” Proc. of SPIE Vol. 6520 65200S-11,(2007) http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=1300463

 

Sean O’Brien, Robert Soper, Shane Best, Mark Mason, “Rules Based Process Window OPC,” Proc. of SPIE Vol. 6925 69251C-9, (2006) 144.206.159.178/FT/CONF/16413389/16413440.pdf

 

“TI sticks with Synopsys for 65nm, 45nm nodes,” EE Times Asia, 09 Jun 2005

“Synopsys’ mask synthesis solutions offer the critical dimension accuracy and near-linear scalability that we require to meet the complex data processing needs for our advanced 65nm and 45nm technology,” said Mark Mason, TI’s resolution enhancement technology manager, in a statement issued by Synopsys. http://www.eetasia.com/ART_8800368629_480200_NT_33f13b4c.HTM

 

David Lammers , Ron Wilson, “Heavy rules hold back 90-nm yield,” EE Times, 03/28/2005

“Eventually, increasing design complexity will no longer be supported by traditional geometric rules,” said Mark Mason, reticle enhancement technology (RET) manager at Texas Instruments Inc. “A model-based, design rule checks solution will be required.” www.isqed.org/English/Archives/2005/EETIMES4-ISQED05.doc

 

Mark Mason, “Mask rule standards: A baby step for DfM,” Solid State Technology, Volume 15, Issue 2 http://www.electroiq.com/articles/mlw/print/volume-15/issue-2/featured/mask-rule-standards-a-baby-step-for-dfm.html

 

Mark Mason, “The real cost of RETs,” Solid State Technology,Volume 12, Issue 2 http://www.electroiq.com/articles/mlw/print/volume-12/issue-2/featured/the-real-cost-of-rets.html